1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a bus drive circuit for driving a bus.
2. Description of Related Art
With the recent increase in the area of a specific part, there has been developed a technology of manufacturing a semiconductor integrated circuit in which the area of the specific part is divided into a plurality of areas or layers. There is an example of a memory macro mounted on a semiconductor integrated circuit. In this case, the memory macro is divided into a plurality of array portions or layers due to an increase in the area of the memory macro. The semiconductor integrated circuit reads data from one of the array portions. With this configuration, it is possible to reduce the current consumption for bus driving, compared to the case in which the data is read from the memory macro.
FIG. 1 is a block diagram of a conventional semiconductor integrated circuit. The semiconductor integrated circuit includes a plurality of array portions 1-1 to 1-n (where n is an integer of 2 or more), first and second data lines LB and LBB, a plurality of bus drive circuits 102-1 to 102-n, a common bus 3, an I/O circuit 4, and a bus holder 5.
The first and second data lines LB, LBB are coupled to each of the array portions 1-1 to 1-n. The bus drive circuits 102-1 to 102-n corresponding to the array portions 1-1 to 1-n are coupled to the first and second data lines LB, LBB of the array portions 1-1 to 1-n, respectively. The common bus 3 is coupled to the bus drive circuits 102-1 to 102-n. The I/O circuit 4 is coupled to the common bus 3. The input and output of the bus holder 5 are coupled to the common bus 3.
For example, the array portions 1-1 to 1-n are memory circuits that are formed by dividing a memory macro into n array portions. Each of the array portions 1-1 to 1-n includes a memory cell array (not shown) in which memory cells for holding data are arranged in a matrix form, word lines (not shown) arranged in the rows of the memory cell array, and first and second bit lines (not shown) arranged in the columns of the memory cell array. The first and second bit lines are coupled to the first and second data lines LB and LBB, respectively.
The first and second data lines LB, LBB are supplied with data from a selected array portion 1-j (where j is an integer satisfying 1≦j≦n), which is one of the array portions 1-1 to 1-n. More specifically, the selected word line corresponding to a specified line address is selected from the word lines of the selected array portion 1-j. Further, a pair of selected first and second bit lines corresponding to a specified column address is selected from the first and second bit lines of the selected array portion 1-j. At this time, the data is read from the memory cell that is coupled to the selected word line and to the selected first and second bit lines, which is one of the memory cells of the selected array portion 1-j. A potential difference is generated between the selected first and second bit lines. As a result, the data is supplied to the first and second data lines LB, LBB.
The common bus 3 is supplied with a bus output signal GBUS representing the data, from a selected bus drive circuit 102-j of the bus drive circuit 102-1 to 102-n. The selected bus drive circuit 102-j is coupled to the first and second data lines LB, LBB of the selected array portion 1-j. The I/O circuit 4 receives the bus output signal GBUS as output data.
The bus holder 5 holds the bus output signal GBUS, and supplies the bus output signal GBUS to the common bus 3. An example of the bus holder 5 is a flip flop circuit.
FIG. 2 is a simplified block diagram of the technology described in Japanese Unexamined Patent Publication No. 2004-213888, showing the configuration of the individual bus drive circuits 102-1 to 102-n shown in FIG. 1.
Each of the bus drive circuits 102-1 to 102-n includes a buffer 7, an amplifier 7, and a logic circuit 108.
The buffer 7 includes a first transistor MPT and a second transistor MNT.
The first transistor MPT is a p-channel metal oxide semiconductor field effect transistor (p-type MOSFET) used as a pull-up transistor. The first transistor MPT is coupled between a power source and the common bus 3.
The second transistor MNT is an n-channel metal oxide semiconductor field effect transistor (n-type MOSFET) used as a pull-down transistor. The second transistor MNT is coupled between the common bus 3 and ground.
The amplifier 6 is supplied in each cycle with a precharge signal PC having a high signal level “H”. The amplifier 6 provides a first potential to the first and second data lines LB and LBB, in response to the precharge signal PC “H” in each cycle. At the same time, the amplifier 6 sets the signal level of the first and second signals D, DB corresponding to the first and second data lines LB, LBB to high level “H”.
Further, the amplifier 6 of the selected bus drive circuit 2-j is supplied with a sense enable signal SE having a high signal level “H”. In response to the sense enable signal SE “H”, the amplifier 6 of the selected bus drive circuit 2-j changes the signal level of the first signal D or the second signal DB from high level “H” to low level “L” when the potential of the first data line LB or the second data line LBB is reduced to a second potential lower than the first potential.
The logic circuit 108 outputs a first control signal P_B “L” when the signal level of the first signal D is high level “H” and the signal level of the second signal DB is low level “L”. In response to the first control signal P_B “L”, the first transistor MPT is turned on and the signal level of the bus output signal GBUS is set to high level “H”.
On the other hand, when the signal level of the first signal D is low level “L” and the signal level of the second signal DB is high level “H”, the logic circuit 108 outputs a second control signal N “H”. In response to the second control signal N “H”, the second transistor MNT is turned on and the signal level of the bus output signal GBUS is set to low level “L”.
The logic circuit 108 includes a first AND circuit 111, a second AND circuit 112, a first output circuit 113, and a second output circuit 114.
The first AND circuit 111 is supplied with the first signal D. Further, the first AND circuit 111 of the selected bus drive circuit 102-j is supplied with an enable signal DEj having a high signal level “H”, during the period from the time when the signal level of the first signal D or the second signal DB is changed from high level “H” to low level “L”, to the time when the precharge signal PC “H” is supplied to the amplifier 6.
The second AND circuit 112 is supplied with a second signal DB. Further, the second AND circuit 112 of the selected bus drive circuit 102-j is supplied with the enable signal DEj having a high signal level “H”.
The first output circuit 113 is an inverter circuit for inverting the output signal P of the first AND circuit 111. The input of the first output circuit 113 is coupled to the output of the first AND circuit 111. The output of the first output circuit 113 is coupled to a gate of the first transistor MPT. When the signal level of the output signal P of the first AND circuit 111 is high level “H”, the signal level of an output signal P_B (where the suffix of “_B” means logical negation and is read “bar B”) of the first output circuit 113 is low level “L”. At this time, the first output circuit 113 outputs the output signal P_B “L” as a first control signal P_B “L”. In response to the first control signal P_B “L”, the first transistor MPT is turned on and the signal level of the bus output signal GBUS is set to high level “H”.
The second output circuit 114 is a buffer circuit. The input of the second output circuit 114 is coupled to the output of the second AND circuit 112. The output of the second output circuit 114 is coupled to a gate of the second transistor MNT. When the signal level N of the second AND circuit 112 is high level “H”, the signal level of an output signal N of the second output circuit 114 is high level “H”. At this time, the second output circuit 114 outputs the output signal N “H” as a second control signal N “H”. In response to the second control signal N “H”, the second transistor MNT is turned on and the signal level of the bus output signal GBUS is set to low level “L”.
With the above configuration, the bus output signal GBUS is supplied to the common bus 3 from the selected bus drive circuit 102-j. In this case, the output of the buffer 7 is in a high impedance state in each of the unselected bus drive circuits other than the selected bus drive circuit 102-j of the bus drive circuits 102-1 to 102-n. 